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Excalidraw Data
Text Elements
IMEM
REG[]
dataW
rsW
rsR1
rsR2
R[rs1]
R[rs2]
ALU
Y
A
B
Inst
Inst[11:7]
Inst[19:15]
Inst[24:20]
32-bit Adder
4
PC
0
1
1
0
0
1
Brach comp
DMMEM
addr
dataW
MemRW
RegWEn
Imm Gen
Inst[31:7]
Inst[31:0]
ImmSel
RegWEn
dataR
1
0
2
PCSel
BSel
ASel
BrEq
BrLt
ALUSel
MemRW
WBSel
Control Logic
IMEM
REG[]
dataW
rsW
rsR1
rsR2
R[rs1]
R[rs2]
ALU
Y
A
B
Inst
Inst[11:7]
Inst[19:15]
Inst[24:20]
32-bit Adder
4
PC
0
1
1
0
0
1
Brach comp
DMMEM
addr
dataW
MemRW
RegWEn
Imm Gen
Inst[31:7]
Inst[31:0]
ImmSel
RegWEn
dataR
1
0
2
PCSel
BSel
ASel
BrEq
BrLt
ALUSel → ADD
MemRW → READ
WBSel
Control Logic
ADD:
IMEM
REG[]
dataW
rsW
rsR1
rsR2
R[rs1]
R[rs2]
ALU
Y
A
B
Inst
Inst[11:7]
Inst[19:15]
Inst[24:20]
32-bit Adder
4
PC
0
1
1
0
0
1
Brach comp
DMMEM
addr
dataW
MemRW
RegWEn
Imm Gen
Inst[31:7]
Inst[31:0]
ImmSel
RegWEn
dataR
1
0
2
PCSel
BSel
ASel
BrEq
BrLt
ALUSel → ADD
MemRW → READ
WBSel
Control Logic
ADDI:
IMEM
REG[]
dataW
rsW
rsR1
rsR2
R[rs1]
R[rs2]
ALU
Y
A
B
Inst
Inst[11:7]
Inst[19:15]
Inst[24:20]
32-bit Adder
4
PC
0
1
1
0
0
1
Brach comp
DMMEM
addr
dataW
MemRW
RegWEn
Imm Gen
Inst[31:7]
Inst[31:0]
ImmSel
RegWEn
dataR
1
0
2
PCSel
BSel
ASel
BrEq
BrLt
ALUSel → ADD
MemRW → READ
WBSel
Control Logic
JALR:
IMEM
REG[]
dataW
rsW
rsR1
rsR2
R[rs1]
R[rs2]
ALU
Y
A
B
Inst
Inst[11:7]
Inst[19:15]
Inst[24:20]
32-bit Adder
4
PC
0
1
1
0
0
1
Brach comp
DMMEM
addr
dataW
MemRW
RegWEn
Imm Gen
Inst[31:7]
Inst[31:0]
ImmSel
RegWEn
dataR
1
0
2
PCSel
BSel
ASel
BrEq
BrLt
ALUSel → ADD
MemRW → READ
WBSel
Control Logic
AUIPC:
IMEM
REG[]
dataW
rsW
rsR1
rsR2
R[rs1]
R[rs2]
ALU
Y
A
B
Inst
Inst[11:7]
Inst[19:15]
Inst[24:20]
32-bit Adder
4
PC
0
1
1
0
0
1
Brach comp
DMMEM
addr
dataW
MemRW
RegWEn
Imm Gen
Inst[31:7]
Inst[31:0]
ImmSel → I
RegWEn
dataR
1
0
2
PCSel
BSel
ASel
BrEq
BrLt
ALUSel → ADD
MemRW → READ
WBSel
Control Logic
LW:
Fetch
Decode
Arithmetic
Memory
Write Back
Embedded Files
315588ca14ba13d16cb20bab0bfa345d6c32f6f6: image_0.png
56d07879f495fe0c3d108f41403ae6db462f8ac3: image_1.png
